Efficient Fast Fourier Transform Processor Design for DVB-H System

Fast Fourier transform (FFT) is the demodulation kernel in the DVB-H system. In this paper, we firstly propose an FFT processor that reduces the power consumption by decreasing the usage of main memory, and timely turning off the unused memory partitions in different sizes of the FFT. Second, the triple-mode conflict-free address generator is proposed to handle the address mapping of all storages in the three-size FFT computations. Then two cost-efficient twiddlefactor coefficient design methods, “Sharing” and “Interpolation-then-Sharing”, are proposed to reduce the area of coefficient storages within the allowable loss of SQNR. These methods can reduce 67% area occupied by coefficient storage at a price of 0.6dB loss of SQNR in our design. Finally, our proposed FFT processor for DVB-H system is implemented by using TSMC 0.18μm 1P6M CMOS technology with core size of 1.886×1.886mm. The minimum latency to operate 8192-point FFT is 805μs at 86MHz clock rate by consuming 75.51mW. For DVB-H system, it processes the 8192, 4096, and 2048-point FFT with clock rates of 79MHz, 75MHz, and 71MHz, and consumes of 67.01mW, 53.16mW, and 39.45mW, respectively.