Efficient Fast Fourier Transform Processor Design for DVB-H System
نویسندگان
چکیده
Fast Fourier transform (FFT) is the demodulation kernel in the DVB-H system. In this paper, we firstly propose an FFT processor that reduces the power consumption by decreasing the usage of main memory, and timely turning off the unused memory partitions in different sizes of the FFT. Second, the triple-mode conflict-free address generator is proposed to handle the address mapping of all storages in the three-size FFT computations. Then two cost-efficient twiddlefactor coefficient design methods, “Sharing” and “Interpolation-then-Sharing”, are proposed to reduce the area of coefficient storages within the allowable loss of SQNR. These methods can reduce 67% area occupied by coefficient storage at a price of 0.6dB loss of SQNR in our design. Finally, our proposed FFT processor for DVB-H system is implemented by using TSMC 0.18μm 1P6M CMOS technology with core size of 1.886×1.886mm. The minimum latency to operate 8192-point FFT is 805μs at 86MHz clock rate by consuming 75.51mW. For DVB-H system, it processes the 8192, 4096, and 2048-point FFT with clock rates of 79MHz, 75MHz, and 71MHz, and consumes of 67.01mW, 53.16mW, and 39.45mW, respectively.
منابع مشابه
Reconfigurable FFT Processor – A Broader Perspective Survey
The FFT(Fast Fourier Transform) processing is one of the key procedure in the popular orthogonal frequency division multiplexing(OFDM) based communication system such as Digital Audio Broadcasting(DAB),Digital Video Broadcasting Terrestrial(DVB-T),Asymmetric Digital Subscriber Loop(ADSL) etc.These application domain require performing FFT in various size from 64 to 8192 point. Implementing each...
متن کاملDesign of an 8192-point Sequential I/O FFT Chip
This paper presents an efficient VLSI design of 8kpoint pipeline fast Fourier transform (FFT) processor capable of producing the sequential order output. The proposed FFT architecture is derived based on the modified delay feed-forward data commutator, and processes the internal dual data streams in the real and imaginary alternate approach. Compared with the general pipeline FFT designs, ours ...
متن کاملHardware-software Codesign of a 14.4mbit - 64 State - Viterbi Decoder for an Application-specific Digital Signal Processor
Viterbi Decoders are employed frequently in wireless radio systems. They often require high computational efforts which can only be handled by dedicated application specific integrated circuits (ASIC)s. Because of their flexibility and speed of development, DSP-based software solutions are desirable, however. Currently available DSPs are not able to provide enough computational power to perform...
متن کاملDesign of Reconfigurable FFT Processor With Reduced Area And Power
Fast fourier transform (FFT) is an efficient implementation of the discrete fourier transform (DFT). The main objective of the project is to implement a reconfigurable FFT processor with reduced power and area in order to provide system designers and engineers with the flexibility to meet different system requirements. This paper proposes a low power and area efficient FFT architecture using Si...
متن کاملDesign and Implementation of 32 Bit FFT using Radix-2 Algorithm
-Fast Fourier Transform (FFT) processing is one of the key procedures in popular Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor for OFDM applications is presented....
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007